CLERECO project

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• October 1, 2013
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Cross-layer Early Reliability Evaluation for the Computing Continuum 

Advanced multifunctional computing systems realized in forthcoming technologies hold the promise of a significant increase of the computational capability that will offer end-users ever-improving services and functionalities (e.g., next-generation mobile devices, cloud services, etc.). However, the same path leading technologies toward these remarkable achievements is also making electronic devices increasingly unreliable, posing a threat to our society depending on computers and electronic devices in every aspect of human activities.

Therefore, the reliability of electronic systems is a key challenge for the whole information and communication technology and must be guaranteed without penalizing or slowing down the final products’ characteristics.

CLERECO research project recognizes Cross-layer Reliability Evaluation as one of the most important and challenging tasks toward this goal. Being able to precisely and early evaluate the reliability of a system means being able to carefully plan for specific countermeasures rather than resorting to worst-case approaches. CLERECO project will be fundamental in developing scaled systems for more than a decade from the present.

The proposed CLERECO framework for efficient reliability evaluation and therefore efficient exploitation of reliability oriented design approaches starting from the early phases of the design process will enable circuit integration to continue at exponential rates and enable the design and manufacture of future systems for the computing continuum at a minimum cost (e.g., up to 50% less area, up to 50% less energy, etc.) contrary to existing worst-case-design solutions for reliability. The applications of such chips will play a major role in our society. They can be seen through the prism of future computing systems ranging from avionics, automobile, smartphones, mobile systems, Personal Computers (PCs), and future servers utilized in the settings of Data Centers, Grid Computing, Cloud Computing, and other types of HPC systems.

If you find this project interesting check out also the other projects of our team 

Related readings:

• Savino, Alessandro; Vallero, Alessandro; Di Carlo, Stefano ReDO: Cross-Layer Multi-Objective Design-Exploration Framework for Efficient Soft Error Resilient Systems IEEE TRANSACTIONS ON COMPUTERS, DOI: 10.1109/TC.2018.2818735
• Di Carlo, Stefano CLERECO, Cross-Layer Early Reliability Evaluation for the Computing cOntinuum, FP7 IMPACT, Vol.2017, pp.71-73, ISSN: 2398-7073, DOI: 10.21820/23987073.2017.3.71
• Vallero, Alessandro; Gizopoulos, Dimitris; DI CARLO, Stefano SIFI: AMD southern islands GPU microarchitectural level fault injector in Proceedings Of The 2017 IEEE 23rd International Symposium On On-Line Testing And Robust System Design (IOLTS 2017), pp.138-144, ISBN: 9781538603512, DOI: 10.1109/IOLTS.2017.8046209
• Chatzidimitriou, Athanasios; Kaliorakis, Manolis; Gizopoulos, Dimitris; Iacaruso, Maurizio; Pipponzi, Mauro; Mariani, Riccardo; DI CARLO, Stefano RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU in Proceedings Of The 47th Annual IEEE/IFIP International Conference On Dependable Systems And Networks Workshop (DSN-W), pp.117-120, ISBN: 978-1-5386-2272-8, DOI: 10.1109/DSN-W.2017.16
• Vallero, Alessandro; Di Carlo, Stefano; Tselonis, Sotiris; Gizopoulos, Dimitris Microarchitecture level reliability comparison of modern GPU designs: First findings in Proceedings Of The IEEE International Symposium On Performance Analysis Of Systems And Software (SPASS 2017), pp.129-130, ISBN: 9781538638897, DOI: 10.1109/ISPASS.2017.7975280
• Savino, A.; Di Carlo, S.; Vallero, A.; Politano, G.; Gizopoulos, D.; Evans, A. RIIF-2: Toward the next generation reliability information interchange format in Proceedings Of The IEEE 22nd International Symposium On On-Line Testing And Robust System Design, IOLTS 2016, pp.173-178, ISBN: 9781509015061, DOI: 10.1109/IOLTS.2016.7604693
• Vallero, A.; Savino, A.; Politano, G.; Di Carlo, S.; Chatzidimitriou, A.; Tselonis, S.; Kaliorakis, M.; Gizopoulos, D.; Riera, M.; Canal, R.; Gonzalez, A.; Kooli, M.; Bosio, A.; Di Natale, G. Cross-layer system reliability assessment framework for hardware faults in Proceedings Of The International Test Conference 2016, pp.1-10, ISBN: 9781467387736, DOI: 10.1109/TEST.2016.7805863
• Vallero, A.; Tselonis, S.; Foutris, N.; Kaliorakis, M.; Kooli, M.; Savino, A.; Politano, G.; Bosio, A.; Di Natale, G.; Gizopoulos, D.; Di Carlo, S. Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview MICROPROCESSORS AND MICROSYSTEMS, Vol.39, pp.1204-1214, ISSN: 0141-9331, DOI: 10.1016/j.micpro.2015.06.003
• Vallero, A.; Savino, A.; Tselonis, S.; Foutris, N.; Kaliorakis, M.; Politano, G.; Gizopoulos, D.; Di Carlo, S. Bayesian network early reliability evaluation analysis for both permanent and transient faults in Proceedings Of The IEEE 21st International On-Line Testing Symposium (IOLTS), pp.7-12, ISBN: 978-1-4673-7905-2, DOI: 10.1109/IOLTS.2015.7229819
• Vallero, A.; Savino, A.; Tselonis, S.; Foutris, N.; Kaliorakis, M.; Politano, G.; Gizopoulos, D.; Di Carlo, S. A Bayesian model for system level reliability estimation in Proceedings Of The 20th IEEE European Test Symposium (ETS), pp.1-2, ISBN: 978-1-4799-7603-4, DOI: 10.1109/ETS.2015.7138745
• RIIF (Reliability Information Interchange Format) – http://riif.iroctech.com/

Project’s details:

• Duration: 2013-2016
• Coordinator: Politecnico di Torino (Italy)
• Partners: National and Kapodistrian University of Athens (Greece) Centre National de la Recherche Scientifique – Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier (France) Intel Corporation Iberia S.A. (Spain) Thales SA (France) Yogitech spa (Italy) ABB AS (Norway)
• Funded by: European Community FP7 Call.
• www:  http://www.clereco.eu