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STT-MRAM model for CACTI simulator

STT-MRAM model for CACTI simulator

A portable and configurable dynamic partial reconfiguration controller for XILINX FPGAs.

RASTA is powerful Fault Simulator architecture for RAM memories developed at Politecnico di Torino.

EF3S is a framework to assess a NAND Flash based memory systems performances (throughput, power, wearout, aging). It’s easy-to-use, automated, highly configurable, and modular.

MarciaTesta++ is an EDA tool for the automatic generation of assembly test programs for both data and instruction cache memories.