Poster presentation on cache timing side-channel attacks at RISC-V Summit Europe 2026
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- June 10, 2026
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Today I had the opportunity to present our poster at RISC-V Summit Europe 2026 (RISC-V International) and it’s been a genuinely memorable experience. 🙌
Our research focuses on cache timing side-channel attacks on RISC-V, leveraging the Zicbom extension to perform Flush+Reload attacks targeting RSA private key recovery. We simulate the full attack in gem5 in Full-System mode, which lets us study the threat under realistic Linux conditions.
Beyond the work itself, what struck me today was how many researchers are seriously engaging with security questions in the RISC-V ecosystem. This architecture is moving fast, and it matters that security is part of the conversation from the ground up.
A big thank you to my supervisors Alessandro Savino and Stefano Di Carlo 😊
#RISCVSummit #RISCV #HardwareSecurity #CacheSideChannel #MicroarchitecturalAttacks #PoliTo #gem5
Shared by: Sadia Shamas
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