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Our Ph.D. student Alberto Carelli is going to give a presentation on “Securing bitstream integrity, confidentiality and authenticity in reconfigurable mobile heterogeneous systems” today at the IEEE International Conference on Automation, Quality and Testing, Robotics 2018 – AQTR’18

Some nice pictures of the hot topic session organized by Prof. Alberto Bosio (LIRMM – France) and Prof. Stefano Di Carlo (Politecnico di Torino) at the 36th IEEE VLSI Test Symposium (VTS 2018) Hayatt Centric Fisherman’s Wharf San Francisco, California USA.

Some nice pictures of the plenary panel organized by Prof. Sule Ozev (Arizona State University – USA) and Prof. Stefano Di Carlo (Politecnico di Torino) at the 36th IEEE VLSI Test Symposium (VTS 2018) Hayatt Centric Fisherman’s Wharf San Francisco, California USA.

Dr. Alessandro Vallero from TestGroup presented our latest study on “Multi-faceted Microarchitecture Level Reliability Characterization for NVIDIA and AMD GPUs” @ 2018 IEEE VLSI Test Symposium, San Francisco, CA, USA (April 22-25, 2018).

We received today an very good news. After more than 1 year from its end, the FP7 Clereco project (http://www.clereco.eu) still produces results in the field of cross-layer reliability analysis.

A paper has been accepted for publication in an upcoming issue of IEEE Transactions on Computers proposing a cross-layer multi-objective design space exploration algorithm developed to help designers when building soft error resilient electronic systems.

We just got the good news that our paper “Trading-off reliability and performance in FPGA-based reconfigurable heterogeneous systems” has been accepted for an oral presentation at the 13th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

We are happy to announce that Testgroup in collaboration with LIRMM (Montpellier, FR) will organize a special session on “How Approximate Computing impacts Verification, Test and Reliability of Integrated Circuits” at the IEEE VLSI Test Symposium 2018 (VTS’18), Hyatt Hotel, San Francisco, CA (USA)  on April 22-25, 2018.

New paper titled “Multi-faceted Microarchitecture Level Reliability Characterization for NVIDIA and AMD GPUs” accepted for publication at the IEEE VLSI Test Symposium 2018 (VTS’18), Hyatt Hotel, San Francisco, CA (USA)  on April 22-25, 2018.

DAUIN PhD students at the end of their studies (XXXX cycle) will present and discuss their research activities.. The event is an opportunity to discover the PhD program in Computer and Control Engineering and to better understand the research activities carried on at DAUIN. It is open to everyone interested.

Alessandro Carelli, Ph.D. student at Politecnico di Torino will present today the results of a study of the effect of side-channel attacks on the SEcube(TM) platform. The presentation will be given at the 15th IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS-2017) in Novi Sad, Serbia.