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Side-channel analysis of SEcube(TM) platform @ EWDTS, 2017

Alessandro Carelli, Ph.D. student at Politecnico di Torino will present today the results of a study of the effect of side-channel attacks on the SEcube(TM) platform. The presentation will be given at the 15th IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS-2017) in Novi Sad, Serbia.

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CPUs fault injection study @ DSN, 2017

Sakis Chatzidimitriou Ph.D. student at University of Athens under Prof. Dimitris Gizopoulos presented yesterday the CPUs fault injection study (on ARM Cortex-A9 CPU) between microarchitecture-level and RT-level result of a collaboration between University of Athens, Politecnico di Torino and Intel/Yogitech in CLERECO FP7 project.

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Clereco project summary published in the HiPEACinfo journal

We are happy to announce that HiPEACinfo vol. 50 is now available for download from the HiPEAC website (https://www.hipeac.net/assets/public/publications/newsletter/hipeacinfo50.pdf). It contains an nice overview of the Clereco results. If you have a LinkedIn account, please consider posting about your article and sharing the link to the magazine via LinkedIn.      

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Paper accepted @ IOLTS 2017

New paper titled “SIFI a reliability evaluation framework for soft-errors built on top of Multi2Sim” accepted for publication at the 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS’17), July 3-5, 2017 in Thessaloniki, Greece.

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Paper accepted @ DSN 2017

New paper titled “RT Level vs. Microarchitecture Level Reliability Assessment: Case Study on ARM Cortex-A9 CPU” accepted for publication at the 47th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2017), June 26-29, 2017 in Denver, CO (USA).

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