Monthly Archives: September 2016

New paper on SIERRA memory simulator now published.

From a collaboration between TestGroup (Politecnico di Torino), TU Delft, University of Siena and Istituto Superiore Mario Boella (ISMB), we have created SIERRA, a simulation environment for precisely evaluating the repair efficiency of an MRA considering different fault signatures and faulty memory configurations. Enjoy reading information about SIERRA our new published.

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Intel to Acquire Movidius

Accelerating Computer Vision through RealSense for the Next Wave of Computing. Interesting announcement from INTEL. Combined with Intel’s Existing Assets, Movidius Technology – for New Devices Like Drones, Robots, Virtual Reality Headsets and More – Positions Intel to Lead in Providing Computer Vision and Deep Learning Solutions from the Device to the Cloud … https://newsroom.intel.com/editorials/josh-walden-intel-editorial/

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DPRC

A portable and configurable dynamic partial reconfiguration controller for XILINX FPGAs.

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RASTA

RASTA is powerful Fault Simulator architecture for RAM memories developed at Politecnico di Torino.

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EFS3

EF3S is a framework to assess a NAND Flash based memory systems performances (throughput, power, wearout, aging). It’s easy-to-use, automated, highly configurable, and modular.

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Marcia Testa++

MarciaTesta++ is an EDA tool for the automatic generation of assembly test programs for both data and instruction cache memories.

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