HARDWARE RESILIENCE: Building Trustworthy Computing Systems from the Microarchitecture Up
At the SMILIES group, we investigate hardware resilience as a key enabler for trustworthy computing systems. Modern platforms—from embedded and automotive devices to RISC-V cloud infrastructures—must operate reliably and securely despite faults, aging, radiation, electromagnetic interference, malicious code, side-channel leakage, and physical attacks.
Our research combines computer architecture, hardware security, reliability analysis, fault injection, micro-architectural monitoring, and machine learning to design systems that can detect, tolerate, and mitigate anomalies early, efficiently, and across the hardware/software stack.
RISC-V Security
Hardware-Based Malware Detection
Fault Injection & Soft-Error Analysis
Side-Channel Leakage Assessment
Hardware Roots of Trust
Funded projects
VITAMIN-V project
Vitamin-V develops a complete RISC-V software stack for cloud services for Trustworthy Development of RISC-V based Cloud Services.
SALVEREMO project
Salveremo: automatically localize dispersed people in mountain remote areas using intelligent UAVs equipped with advanced sensing devices.
Repositories on GitHub
Relevant Publications
- L. Mannella, S. Di Carlo, A. Savino, “Experimental Analysis of FreeRTOS Dependability through Targeted Fault Injection Campaigns,” Proceedings of the 2026 IEEE 29th International Symposium on Design and Diagnostics of Electronic Circuits and Systems — DDECS 2026, pp. 1–6, 2026. DOI: 10.1109/DDECS69233.2026.11520990.
- C. Pegoraro Chenet, A. Savino, S. Di Carlo, “Zero-Day Hardware-Supported Malware Detection of Stack Buffer Overflow Attacks: An Application Exploiting the CV32e40p RISC-V Core,” IEEE Latin American Test Symposium — LATS 2025, pp. 1–6, 2025. DOI: 10.1109/LATS65346.2025.10963939.
- E. Magliano, A. Savino, S. Di Carlo, “Real-time Embedded System Fault Injector Framework for Micro-architectural State Based Reliability Assessment,” Journal of Electronic Testing, vol. 41, pp. 193–208, 2025. DOI: 10.1007/s10836-025-06170-w.
- B. Farnaghinejad, A. Porsia, A. Ruospo, A. Savino, S. Di Carlo, E. Sanchez, “Late Contribution: VeriSide: A Modified Verilator for Leakage Assessment at the RTL Level,” IEEE Latin American Test Symposium — LATS 2025, pp. 1–2, 2025. DOI: 10.1109/LATS65346.2025.10963943.
- B. Farnaghinejad, A. Porsia, A. Ruospo, A. Savino, S. Di Carlo, E. Sanchez, “Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide,” RESCUER Workshop, co-located with IEEE European Test Symposium 2025, 2025. DOI: 10.48550/arXiv.2512.21362.
- F. Oberti, S. Di Carlo, A. Savino, “CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN Bus,” IEEE International Symposium on On-Line Testing and Robust System Design — IOLTS 2025, pp. 1–5, 2025. DOI: 10.1109/IOLTS65288.2025.11116886.
- M. Alonso, D. Andreu, R. Canal, S. Di Carlo, O. Chatzopoulos, C. Pegoraro Chenet, J. Costa, A. Girones, D. Gizopoulos, G. Papadimitriou, E. Morancho, B. Otero, A. Savino, “Special Session: Security and RAS in the Computing Continuum,” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems — DFT 2024, 2024. DOI: 10.1109/DFT63277.2024.10753548.
- E. Magliano, A. Carpegna, A. Savino, S. Di Carlo, “A Micro Architectural Events Aware Real-Time Embedded System Fault Injector,” IEEE Latin American Test Symposium — LATS 2024, pp. 1–6, 2024. DOI: 10.1109/LATS62223.2024.10534595.
- C. Pegoraro Chenet, A. Savino, S. Di Carlo, “A Survey on Hardware-Based Malware Detection Approaches,” IEEE Access, vol. 12, pp. 54115–54128, 2024. DOI: 10.1109/ACCESS.2024.3388716.
Involved team
